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دانلود رایکان مقاله انگلیسی ISI با موضوع معماری جمع کننده ترکیبی با بازدهی انرژی بالا

عنوان فارسی مقاله:

معماری جمع کننده ترکیبی با بازدهی انرژی بالا

عنوان انگلیسی مقاله:

Energy efficient hybrid adder architecture

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1. Introduction
With the explosion of mobile computers and other portable devices, low-power and low-energy design became a must. Power and energy go hand in hand; power reduction leads to lower energy consumption over a fixed time span. Arithmetic circuits are considerable contributors of power and energy in computation intensive applications and require therefore a careful power-delay design tradeoff [1; Ch. 26]. Addition is a fundamental arithmetic operation for which a wide variety of algorithms and methods exist [2]. Many alternatives for adder architectures have been invented [1 Ch. 5–8] with emphasis on their VLSI circuit implementation [3]. Carrylookahead (CLA) [1 Ch. 6], carry-skip [4], and carry-select [5] adder architectures, among many others, present different area-delaypower tradeoffs. Several works studied energy-efficient adders. While in [6,7] basic full-adder cells were proposed, in [8,9] carrypropagate adders were compared. It was noted in [9] that faster arithmetic circuits can be more energy efficient, a direction taken by our work.

1. مقدمه